VLSI and Microelectronics, Device Physics, A/D Communication

• Elected on February 7, 2015 as Senior Member of IEEE.
• Biography is included in the Marquis Who's who in the World in 2010, 2016, 2019, 2020.
• Life Member of IETE approved by the M&CC Sub-Committee Meeting
• Received National scholarship from the Govt. of India, Ministry of HRD for securing 1st class marks in BSc Physics Hons as per merit list.
• Selected and Approved as Scientific and Technical Committee member of WASET in 2015.
• Selected as Senior Member of IETI, Hong Kong on August 23, 2015.
• Selected on May 19, 2018 as recipient of 2018 Albert Nelsen Marquis Lifetime Achievement Award by Marquis Who’s Who Selection Committee.
• Main organizer of many IEEE Conferences /Seminars/Workshops/Technical talks /Mini colloquium as General Chair /Technical Program Chair /Organizing Chair. Member of Technical program committee of DEVIC international conference. Session Chair and Session Coordinator of VLSI DCS 2020. Session Chair of DEVIC international conference.
• Received Letter of Appreciation from MoE’s Innovation Cell, Government of India for the continuous support and contribution towards building the innovation and entrepreneurship culture development in MSIT and also extending support to help other IIC institutions towards growth of the IIC network during the academic year 2021-22.

Work Experience:
1. Presently working as Associate Professor in the Department of Electronics & Communication Engineering since December 12, 2002.
Details of promotion in Meghnad Saha Institute of Technology:
a) Worked as Lecturer from 12/12/2002 to 31/12/2007.Service in MSIT confirmed in December 2003
b) Worked as Senior Lecturer from 1/1/2008 to 30/6/2010.
c) Worked as Assistant Professor with AGP 7000 from 1/7/2010 to 30/6/2012.
d) Worked as Assistant Professor with AGP 8000 from 1/7/2012 to 30/6/2022
e)Worked as the Head of the Department of ECE of Meghnad Saha Institute of Technology from June 17, 2019 to March 1, 2021.
f) Currently working as Associate Professor from July 1, 2022 to till date.

2. Worked as Guest Faculty (external), PhD Supervisor, M. Tech and PhD thesis examiner of Jadavpur University for a period of 4 years after completing PhD.

3. Worked as Graduate Engineer Trainee at Webfil Ltd, a Govt. of India enterprise for 6 months.

Research Experience:
Carried out research in the domain of short channel effects in submicron MOSFETS and their remedies from 2008 to 2013 at ETCE Department of Jadavpur University as PhD scholar.

Administrative responsibilities:

1) Current Officer In-Charge (MSIT, College code 142) of MAKAUT semester examination since June 2024. Worked as Supervisor and Central Examination Coordinator of West Bengal University of Technology semester examination of Meghnad Saha Institute of Technology for 1 and 2 semesters respectively.

2) Presiding Officer of GATE and JAM 2016 at Meghnad Saha Institute of Technology

3) Worked as Chair of all Departmental committees and Member of Academic Administrative committee Anti Ragging Core committee and other central committees of MSIT from June 17, 2019 to March 1, 2021 as HOD. Member of Anti Ragging central committee, Central Purchase committee, Infrastructural Development committee, Central Library committee, Internal Quality Assurance committee of MSIT from October 2020 to March 1, 2021. Organized Domain knowledge trainings and Industrial trainings in online and offline mode. Organized webinars and Technical talks during lockdown period. Organized seminars, workshops, Technical talks during March 2020-February 2021 lockdown period.

4) Worked as member of Central Routine, Examination, Website, Mentorship, Research and Development committees of MSIT for 12 years. Class Coordinator of 2nd and 3rd year ECE for over 10 years. Departmental NBA coordinator for 3 years, Departmental Project, Seminar, workshops Coordinator for over 12 years. Departmental Disciplinary committee member for 3 years. Currently an Innovation Ambassador of IIC MSIT for the past 3 years.

5) Currently working as Innovation ambassador of IIC MSIT, Class Coordinator of ECE 3rd year, Convener of ARIIA committee, Convener of NIRF committee, Member of Anti-ragging core committee, Member of Central Finance Committee, Convener DAC ECE, Convener of PAC ECE, Member of Disciplinary committee of ECE, Lab In charge of Analog Communication lab

6) Subjects taught: Analog Communication, Analog Electronics, Analog and Digital Electronics, Principles of Communication Engineering, Communication Engineering and Coding theory, Basic Electronics, Circuit Theory and Networks, Renewable Energy, Wireless Sensor Network, Digital Communication, Electronic Devices and their corresponding labs. Student feedback : 4.9/5, 4.6/5 in Departmental subjects. 4.46/5 and 4.43/5 in non Departmental theory subjects. 4.9/5 and 4.6/5 in Departmental labs.

7) Guided over 38 final year Project groups in their B. Tech final year Projects. Also guided over 34 Seminar groups of ECE 3rd year. Guided 6 groups of ECE 3rd year students in mini projects. Guided students of ECE DEPT, MSIT in publishing 8 International Journals and 8 International Conference papers, 4 books.

8) Worked as Centre-in-charge of WBJEEB in April 27, 2025

University semester and CA examination paper setter
Maulana Abul Kalam Azad University of Technology odd and even semester examination paper setter of the following subjects of M.Tech in Electronics and Communication Engineering in 2021-22 and 2022-23 with specialization in VLSI Design:
1) Semiconductor Device Modeling
2) Waste to Energy
3) RF VLSI Design

University external moderator
Worked as External Moderator for even Semester Examinations 2023-24 of Brainware University on May 2, 2024 for B.Tech.(RA) 2021 PCC-ECR602 Industrial Robotics and Automation, B.Tech. (RA) 2021 PEC-ECR601B Nano Electronics, M.Tech. (RA) 2023_2022 PEC-MIRA201 A Machine Learning in Robotics, B.Tech.(ME) 2021 PCC-ME602 Mechatronics, B.Tech. (ECE) 2020 PEC-ECEL601A Nano Electronics, B.Sc.(ANCS) 2022_2021 GEEC201 Communication System.

PhD(Engg.) from Jadavpur University in July 2013, M.Tech in VLSI and Microelectronics from Jadavpur University in 2008, B.Tech in Radiophysics and Electronics in 2001, B.Sc(Physics. Hons.) from Ramkrishna Mission Vivekananda Centenary College,Raharah in 1998

1) Manash Chanda, Sankalp Jain, Swapnadip De, C.K.Sarkar "IMPLEMENTATION OF SUBTHRESHOLD ADIABATIC LOGIC (SAL) FOR ULTRA- LOW POWER APPLICATION", DOI:10.1109/TVLSI.2014.2385817,IEEE Transactions on Very Large Scale Integration Systems, published in IEEE Xplore on 22nd January, 2015, ScopusSJR:0.62, Impact factor: 1.22.

2) Manash Chanda, Prithu Dey, Swapnadip De, C.K.Sarkar "Novel Charge Plasma Based Dielectric Modulated Impact Ionization MOSFET as a Biosensor for Label-Free Detection", doi:10.1016/j.spmi.2015.08.013, accepted in Superlattices and Microstructures, Elsevier on August 15, 2015, Impact factor: 1.98.

3) A.Sarkar, Swapnadip De, Anup Dey, C.K.Sarkar "Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model", Journal of Computational Electronics (Springer), volume 11, no.2, pp.182-195, 2012, available in Springerlink (DOI: 10.1007/s10825-012-0396-9), Scopus SJR: 0.46, Impact factor: 1.52.

4)A.Sarkar,Swapnadip De,Anup Dey,C.K.Sarkar "1/f noise and analogue performance study of short-channel cylindrical surrounding gate MOSFET using a new subthreshold analytical pseudo-two-dimensional model", IET Circuits, Devices & Systems,vol. 6,issue 1,January 2012,pp.28-34,available in IEEE Xplore, Impact factor:0.91.

5)A.Sarkar,A.K.Das,Swapnadip De,C.K.Sarkar "Effect of gate engineering in double gate MOSFETs for analog/RF applications", Microelectronics Journal, Elsevier,vol.42,issue 11,pp. 873-882,November 2012, Scopus SJR:0.33, Impact factor:0.92.

6) Swapnadip De, A.Sarkar, C.K.Sarkar "Modelling of parameters for asymmetric halo and symmetric DHDMG n-MOSFETs", International Journal of Electronics, Taylor & Francis, UK, vol.98, no.10, October 2011, pp.1365-1381, Scopus SJR: 0.30, Impact factor: 0.75.

7)Swapnadip De,A.Sarkar,C.K.Sarkar"Modelling of Characteristic Parameters for Asymmetric DHDMG Mosfet", WSEAS Transactions on Circuits and Systems, Greece, volume 11, issue 11, November 2012, pp. 371-380,Scopus SNIP: 0.27, Scopus SJR:0.16, 2 year cites/doc equivalent to Thomson reuter Impact factor:0.41.

8) M.Chanda, Swapnadip De, C.K.Sarkar "Modeling of Characteristic Parameters for Nano-scale junctionless Double Gate MOSFET considering Quantum Mechanical Effect", Journal of Computational Electronics (Springer), article first published online on December 4,2014, DOI: 10.1007/s10825-014-0648-y, Scopus SJR: 0.46, Impact factor: 1.52.

9) M.Chanda, Swapnadip De, C.K.Sarkar "DESIGN AND ANALYSIS OF 32 BIT CLA USING ENERGY EFFICIENT ADIABATIC LOGIC FOR ULTRA LOW-POWER APPLICATION", Journal of Circuits, Systems, and Computers, World Scientific Publishing, vol. 24, issue 10, September 2015, Impact factor: 0.33.

10)A.Sarkar,Swapnadip De,C.K.Sarkar "Asymmetric halo and symmetric Single-Halo Dual –Material Gate and Double-Halo Dual –Material Gate n-MOSFETs characteristic parameter modeling", International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, published online in Wiley Online Library(DOI:10.1002/jnm.1829), vol.26, issue 1, pp.41-55,January 2013, Scopus SJR: 0.27, Impact factor:0.63.

11)A.Sarkar,Swapnadip De,Anup Dey,C.K.Sarkar "A new analytical subthreshold model of SRG MOSFET with analogue performance investigation", International Journal of Electronics, Taylor & Francis,UK,vol.99,no.2,December 2011,pp.267-283,Scopus SJR: 0.30,Impact factor:0.75.

12) Manash Chanda, Swapnadip De, C.K.Sarkar "Modeling of Parameters for Nano-Scale Surrounding Gate nMOSFET considering Quantum Mechanical Effects", International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, vol. 27,pp. 883-895,Article firstpublished online in Wiley Online Library (DOI: 10.1002/jnm.1965) on 18.12.2013,Scopus SJR: 0.27, Impact factor:0.63.

13) Swapnadip De, A.Sarkar, C.K.Sarkar “Application of Gaussian profile based DHDMG n-MOSFETs on deep submicron microelectronic circuits", International Journal of Applied Engineering Research, Research India Publication vol.7, no.5, pp.471-483, March 2012, ScopusSJR: 0.13, 2 year cites/doc equivalent to Thomson reuter Impact factor: 0.123.

14) Swapnadip De, A.Sarkar, C.K.Sarkar "Quasi Fermi Potential Based Analytical Sub Threshold Drain Current and Transconductance Model for Practical DHDMG n-Mosfet", International Journal of Applied Engineering Research, Research India Publication, vol.7, no.7, pp.795-811, July 2012, Scopus SJR:0.13, 2 year cites/doc equivalent to Thomson reuter Impact factor: 0.123.

15) Manash Chanda, Tanushree Ganguli, Rounak Dutta, Shouvik Mukhopadhyay,Swapnadip De "Design and Implementaion of 8T Full Adder for High Speed Application”, Advances in Industrial Engineering and Management (“AIEM”) published by American Scientific Publishers (ASP), USA ) ISSN: 2222-7059 (Print); EISSN: 2222-7067 (Online), vol. 5, issue 1.

16) Manash Chanda, Tanushree Ganguli, Rounak Dutta, Shouvik Mukhopadhyay,Swapnadip De, "Design and Implementation of 8x8 Adiabatic Multiplier using Single Phase Adiabatic Dynamic Logic”, Advances in Industrial Engineering and Management (“AIEM”) published by American Scientific Publishers (ASP), USA ) ISSN: 2222-7059 (Print);EISSN: 2222-7067 (Online), vol. 5, issue 1.
17) Aatrayee Das, Prachi Agarwal, Subhra Sarkar, Sudeshna Mukherjee, Manash Chanda, Swapnadip De " Modelling of Surface Potential and Drain Current for linearly doped short channel nMOSFET with Inner Fringing Field”,Advances in Industrial Engineering and Management (“AIEM”) published by American Scientific Publishers (ASP), USA ) ISSN: 2222-7059 (Print);EISSN: 2222-7067 (Online), vol. 5, issue 1, pp. 1-6.

18)Sudeshna Mukherjee, Subhra Sarkar, Prachi Agarwal, Aatrayee Das, Manash Chanda, Swapnadip De "Modelling of the basic parameters for Gaussian doped Symmetric Double Halo Dual Material Gate n-MOSFET ”, Advances in Industrial Engineering and Management (“AIEM”) published by American Scientific Publishers (ASP), USA ) ISSN: 2222-7059 (Print);EISSN: 2222-7067 (Online), vol. 5, issue 1, pp. 7-11.

19)Swapnadip De,A.Sarkar,C.K.Sarkar "Modeling of Thermal and Flicker Noise for Double Gate MOSFET", Journal of Electron Devices, France, volume 8, 2010, pp. 320-324, indexed in googlescholar, ISI Indexing under process, ISRA Journal Impact Factor: under process.

20)Swapnadip De,A.Sarkar "Modeling of Characteristic Parameter for Submicron MOSFET", The IUP Journal of Electrical & Electronics Engineering, ICFAI University Press,vol.5, issue no.3, pp.67-76, July 2012, indexed in EBSCO database and googlescholar.

21) Swapnadip De, A.Sarkar, C.K.Sarkar "Fringing Capacitance based surface potential model for pocket DMG n-MOSFETs", Journal of Electron Devices, France, volume 12, 2012, pp. 704-712, indexed in googlescholar,ISI Indexing under process, ISRA Journal Impact Factor: under process .

22) Debarati Das,Swapnadip De, Manash Chanda, C K Sarkar "Modelling of sub threshold surface potential for short channel Double gate Dual Material Double Halo MOSFET" ,The IUP Journal of Electrical & Electronics Engineering, ICFAI University Press, vol.7 issue no.4, pp. 19-42, October 2014, indexed in EBSCO database and googlescholar,.

23)SwapnadipDe,A.Sarkar,C.K.Sarkar"Threshold voltage and drift-diffusion theory based drain current model for pocket-DMG n-MOSFETs with inner fringing field", Journal of Electron Devices, France, volume 12, 2012, pp. 767-771, indexed in googlescholar, ISI Indexing under process, ISRA Journal Impact Factor: under process.

24) Swapnadip De,Angsuman Sarkar "A study of the Characteristic Parameters for Deep-Submicron MOSFETs",The IUP Journal of Electrical & Electronics Engineering, ICFAI University Press,vol.7 issue no.1,pp. 41-52,January2014,

25) Swapnadip De, Mainak Bhattacharya, Aditi Kumari, Poulami Dutta, Ishita Gupta "Comparative study of Surface Potential for non conventional Double Gate MOSFETs", International Journal of VLSI Design and Technology, Journalspub, vol. 1, issue 1, pp. 1-19

26) Swapnadip De, Aditi Kumari, Poulami Dutta, Ishita Gupta, Mainak Bhattacharya, "A Review of Subthreshold Surface Potential for Single Gate Dual Material Double Halo MOSFET", International Journal of VLSI Design and Technology, Journalspub, vol. 2, issue 1, pp. 1-20

27) Swapnadip De, Angsuman Sarkar, “Thermal and Flicker Noise Modeling of a Double Gate MOSFET”, International Journal on Electronic and Electrical Engineering (IJEEE), ISSN 0974-2042, Scientific Engineering Research Corporation, India, Summer edition 2010, March-May2010,Vol:10,No:01,pp.24-28

28) Swapnadip De,Angsuman Sarkar,Chandan Kumar Sarkar, “Modeling of subthreshold surface potential in short channel, LAC, Double Halo & DMG MOSFETs with inner fringing fields”, InternationalJournal on Electronic and Electrical Engineering (IJEEE), ISSN 0974-2042, Scientific Engineering Research Corporation, India, Spring edition 2009, Vol:01, No: 01,pp.133-141

29) Swapnadip De,Angsuman Sarkar,Chandan Kumar Sarkar, “Subthreshold surface potential model for a single-Halo dual-material gate MOSFET”, International Journal on Electronic and Electrical Engineering (IJEEE), ISSN 0974-2042,Scientific Engineering Research Corporation,Springedition2009,Vol:01,No:01,pp.14-18

30) Angsuman Sarkar, Swapnadip De,Chandan Kumar Sarkar, “Subthreshold Surface Potential Model for a Double-Halo Dual-Material GATE And a Single Halo Dual-Material GATE MOSFET”, International Journal on Electronic and Electrical Engineering (IJEEE), ISSN 0974-2042, Scientific Engineering Research Corporation,India,Spring edition 2009,Vol.:02,no.:02,pp.25-33

31) Akashdeep Mazumder, Saim Aktar, Anamika Kumari, Aaswas Ganguly, Swapnadip De "Study of characteristic parameters for Channel and Gate Engineered Double Gate MOSFET considering Gaussian doping and Inner Fringing Capacitance", accepted in Advances in Industrial Engineering and Management (“AIEM”) published by American Scientific Publishers (ASP), USA ) ISSN: 2222-7059 (Print);EISSN: 2222-7067 (Online).

32) Swapnadip De, A Sarkar, S Das, "A review of surface potential of short channel MOSFETs in subthreshold regime ", International Journal of Science & Engineering Development Research (www.ijsdr.org), ISSN:2455-2631, Vol.8, Issue 8, page no.204 - 217, August-2023, Available :http://www.ijsdr.org/papers/IJSDR2308030.pdf

33) Swapnadip De, Srijan Das, Anirban Choudhary, Sudeshna Sarkar, "Review of Characteristic parameters for non-conventional Double Gate MOSFETs", IJRAR - International Journal of Research and Analytical Reviews (IJRAR), E-ISSN 2348-1269, P- ISSN 2349-5138, Volume.11, Issue 1, Page No pp.303-312, January 2024, Available at : http://www.ijrar.org/IJRAR24A1568.pdf

34) Swapnadip De, Debasmita Ghosh, Debjani Satpati, "Review of modelling of surface potential for channel and gate engineered MOSFETs in subthreshold regime", IJRAR - International Journal of Research and Analytical Reviews (IJRAR), E-ISSN 2348-1269, P- ISSN 2349-5138, Volume.11, Issue 3, Page No pp.221-226, July 2024, Available at : http://ijrar.org/viewfull.php?&p_id=IJRAR24C1151

Membership/Office Bearer of Professional Organizations
1) Senior Member of IEEE( SM90381711)
2) Senior Member of IETI, Hong Kong (2015082318)
3) Vice Chairman and Secretary of IEEE EDS Kolkata Chapter for 3 years from January 2015 to December2017.
IEEE EDS Kolkata Chapter Executive committee: http://ewh.ieee.org/r10/calcutta/eds/executive-committee.html
4) Executive Committee Member of IEEE Electron Devices Society, Kolkata Chapter from December 2013 to December 2019.
5) Life Member of IETE (M237756L)
6) Scientific and Technical committee member of WASET
7)Executive Committee Member of IEEE Kolkata Section for 3 years
8) Founder Chapter Advisor of IEEE EDS MSIT Student Branch Chapter from July 2015 to February 17, 2017. Branch Counselor of IEEE MSIT SB since February 18, 2017.
9) Honorary Member of Board of Studies of All India Eminent Faculty Council of Engineering, Management and Technology, recognized and licensed organization under Ministry of Corporate Affairs, Government of India since 28/11/2020.
10) Honorary Member of All India Applied information technology development association, recognized and licensed organization under Ministry of Corporate Affairs, Government of India since 29/11/2020.

Joint Supervisor of 1 candidate. Completed in 2018.

UG: Analog Communication, Analog Electronics, Electronic Device, Digital Communication, WSN, Circuit theory and Networks, Basic Electronics, A/D Electronics
PG: RF VLSI Design, Semiconductor device modelling , Waste to energy

IEEE Technical Talk/IIC talks presented
1) Presented an IEEE Invited Technical Talk on "Fundamentals of Short Channel Effect in MOSFETs and their remedies" in a One Day Seminar on “Retrospect & Prospects of Radio Science and Microelectronics", organized by IEEE Electron Devices Society KGEC Student Branch Chapter, IEEE GRSS Kolkata Chapter and Department of Electronics & Communication Engineering, Kalyani Government Engineering College on October 8, 2015 at Kalyani Government Engineering College.

2) Presented an IEEE Invited Technical Talk on"Short Channel Effects in MOSFET", organized by IEEE Electron Devices Society, Kolkata Chapter and IEEE HITK Student Branch Chapter at Heritage Institute of Technology, Kolkata, India in March 2013.

3) Delivered a talk on "Innovation : A 360 degree perspective ", as Innovation Ambassador of IIC MSIT, organized by IIC MSIT, Government of India on 26/8/2021.

4) Delivered a talk on "Building an innovation/product fit for market" as Innovation Ambassador of IIC MSIT, on 25/8/2021, organized by IIC MSIT, Government of India.

5) Delivered a talk on "Innovation : A 360 degree approach ", as Innovation Ambassador of IIC MSIT, organized by IIC MSIT, Government of India on 29/9/2021 for Induction program of CSE MSIT.

6) Delivered a talk on "Role of innovation in Engineering ", as Innovation Ambassador of IIC MSIT, organized by IIC MSIT, Government of India on 30/9/2021for Induction program of ECE MSIT.

List of Conference Presentations
1) Swapnadip De, A.Sarkar, N.Mohankumar, C.K.Sarkar “Effect of Fringing Field in Modeling of Subthreshold Surface Potential in Dual Material Gate (DMG) MOSFETs", Proceedings of ICECE 2008, vol.1, pp. 148-151, 20-22 December 2008, Dhaka, Bangladesh, ISBN: 978-1-4244-2014-8,available in IEEE Xplore, Scopus SJR: 0.11, 2 year Cites/doc equivalent to Thomson Reuter Impact factor: 0.

2) A.Sarkar, Swapnadip De, N.Mohankumar, C.K.Sarkar, S.Baishya “Effect of Fringing Fields on Subthreshold Surface Potential of Channel EngineeredMOSFETs", Proceedings of TENCON 2008 ,vol.1,pp.1-6,19-20 November 2008, Hyderabad, India, Publisher: Institute of Electrical and Electronics Engineers Inc.. Publishing country: United States, ISSN: 21593450, ISBN:978-1-4244-2408-5, available in IEEE Xplore, Scopus SJR: 0.11, 2 year Cites/doc equivalent to Thomson Reuter Impact factor: 0. 3 year Cites/doc: 0.11.

3)M.Chanda, Swapnadip De, A.Ghosh, D.Banerjee, P.Biswas “A Novel Design of Low Voltage Full Adder using 14 MOSFETs", Proceedings of International Conference MS'07,December 3-5,2007,University of Calcutta, West Bengal, India.

4)A.Sarkar, Swapnadip De, N.Mohankumar, C.K.Sarkar “Surface Potential Model in Short Channel MOSFET including effect of inner Fringing Field operating in Subthreshold region", Proceedings of National Conference on Recent Development in Applied Mathematical Science and Engineering,vol.1,pp.1-8,20-22 February 2009,Jalpaiguri Government Engineering College, West Bengal, India.

5)Swapnadip De, M.Chanda, A.Sarkar “Analytical Sub-threshold Surface Potential and Drain Current Model for Linearly Doped Double Halo DMG MOSFET", Proceedings of DRDO and CSIR sponsored 2nd National Conference on Advanced Communication Systems and Design Techniques (NCACD 2012),vol.1,pp.67-70,29-30 September2012,Haldia Institute of Technology, India.

6)M.Chanda,Swapnadip De “Design and Implementation of Ultra Low-Power 8x8 Adiabatic Multiplier using SPADL", Proceedings of DRDO and CSIR sponsored 2nd National Conference on Advanced Communication Systems and Design Techniques (NCACD2012),vol.1, pp.29-30 September2012,Haldia Institute of Technology, India.

7) Dr.Swapnadip De, Dr. Angsuman Sarkar, Manash Chanda and Dr. Chandan Kumar Sarkar "Study of Surface Potential and Threshold Voltage for non-uniformly doped DHDMG n-Mosfet",Proceedings of IEEE EDS Kolkata Chapter sponsored 4th International Conference on Technical and Managerial Innovation in Computing and Communications in Industry and Academia (IEMCON 2013), pp.56-60, August 23,2013, Eagle Eye Publications, India, organized by IEM, Kolkata.

8)Manash Chanda, Prithu Dey, Swapnadip De, C K Sarkar "Modelling of RF Parameters for Nano-scale junctionless Double Gate MOSFET considering Fringing Effect", Proceedings of 3rd International Conference on Nanotechnology (NANOCON 2014), October 14-15, 2014, Pune, India, organized by Bharati Vidyapeeth University in association with North Carolina State University, The University of Tokushima, Tuskegee University and MET.

9) Manash Chanda, Indu Gopal Maity, Sabyasachi Chandra, T Ganguli, Swapnadip De, C K Sarkar "Implementation of 8 bit CLA using Single-Clock Powered Energy-Efficient Adiabatic Logic" Proceedings of IEEE EDS Kolkata Chapter sponsored 4th International Conference on Computing, Communication and Sensor Network (CCSN 2015), December 24-25, 2015, Kolkata. The paper was selected as Best Paper of the Conference by the Judges.

10) Aatrayee Das, Prachi Agarwal, Subhra Sarkar, Sudeshna Mukherjee, Manash Chanda, Dr.Swapnadip De"Characteristic Parameter Modelling of Non-uniformly Doped Channel and Gate Engineered MOSFET with Inner Fringing Fields”, Proceedings of International Conference on DevIC 2016,ISBN: 978-93-5258-825-1, pp. 11-14, March 29-30, 2016, Kalyani Government Engineering College, Kolkata.

11) Sudeshna Mukherjee, Subhra Sarkar, Prachi Agarwal, Aatrayee Das, Manash Chanda, Dr.Swapnadip De"Study of Surface Potential and Threshold Voltagefor non-uniformly doped DHDMG n-MOSFET”, Proceedings of International Conference on DevIC 2016,ISBN: 978-93-5258-825-1, pp. 3-6, March 29-30, 2016, Kalyani Government Engineering College, Kolkata

12) Rounak Dutta, Shouvik Mukhopadhyay, Tanushree Ganguli, Manash Chanda, Swapnadip De "Ultra Low-Power 88 Adiabatic Multiplier using Single Phase Adiabatic Dynamic Logic”, Proceedings of International Conference on DevIC 2016, March 29-30, 2016, Kalyani Government Engineering College, Kolkata.

13) Rounak Dutta, Shouvik Mukhopadhyay, Tanushree Ganguli, Manash Chanda, Swapnadip De" High Speed 8T Full Adder Design using Novel XOR”, Proceedings of International Conference on DevIC 2016, March 29-30, 2016, Kalyani Government Engineering College, Kolkata.

14) Sandipta Mal, Anindita Poddar, Akash Mondal, Manash Chanda, Dr.Swapnadip De, "Design and Implementation of Low Power 7-segment Decoder in Near-Threshold Regime", Proceedings of Micro 2016 (Junior), 3rd International Conference Micro 2016 organized by MAKAUT, in association with IASTM, IEEE EDS Kolkata Chapter, July 9-10, 2016, Science City, Kolkata, pp. 1-3.

15) Sandipta Mal, Swapnadip De, Manash Chanda et. al., "Design and Analysis of Nano-dimensional Full Adder in Near Threshold Regime for Low Power Application".Proceedings of IEEE EDS Kolkata Chapter Technically cosponsored 1st International Conference NANOBIOCON 2016 on October 3-5, 2016 at Science City, Kolkata, abstract in pp. 101.

16) Srijan Das, Anirban Choudhury, Soham Ghosh, Sudeshna Sarkar, M Chanda, Swapnadip De "Parameter Modeling of linearly doped Double Gate MOSFET with high-k dielectrics" Proceedings of 2nd International Conference DevIC 2017, March 23-24, 2017, to be included in IEEE Xplore

17) Anirban Chowdhury, Sandipta Mal, Shruti Goswami, Akash Mondal, Swapnadip De, Manash Chanda, “Adiabatic Implementation of Reversible Architecture”, Proceedings of 2nd International Conference DevIC 2017, March 23-24, 2017, to be included in IEEE Xplore.